This is how it now works. A timer running at the sampling frequency triggers the conversion of the two ADC channels and the simultaneous computation of a new signal sample in the DDS sine wave generator. (No changes here.)

The new sample is output by the DAC and also fed into the reference channel of the sample buffer. The other two channels of the sample buffer are fed by the outputs of the two ADCs. To compute amplitude and phase of the channel signals we take the DFT of the buffer contents and get the complex values U, I, R. By comparing U with R and I with R we can compute the absolute phases of the voltage and current signals. With an ideal analog frontend we would not need R and could compute the impedance as Z = U / I. But as the analog frontend introduces additional phase shifts we need to take these into account. To measure the phase shifts in a calibration procedure we therefore need R as a phase reference.

The difference between the new architecture and the old one is mainly in how the filtering is done. Both compute a DFT on the signal frequency but the original method averaged the output using a downsampling filter with a filter length unrelated to the signal whereas the new one averages over exactly an integer number of signal periods in the sample buffer which lead to significantly better results.