// Copyright (C) 2025  Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and any partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
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// to the terms and conditions of the Altera Program License 
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
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// Generated by Quartus Prime Version 24.1 (Build Build 1077 03/04/2025)
// Created on Wed Apr 30 13:42:39 2025

Fifo Fifo_inst
(
	.clk(clk_sig) ,	// input  clk_sig
	.data_push(data_push_sig) ,	// input [7:0] data_push_sig
	.push(push_sig) ,	// input  push_sig
	.pop(pop_sig) ,	// input  pop_sig
	.fifo_full(fifo_full_sig) ,	// output  fifo_full_sig
	.fifo_empty(fifo_empty_sig) ,	// output  fifo_empty_sig
	.data_pop(data_pop_sig) 	// output [7:0] data_pop_sig
);

defparam Fifo_inst.FIFOSIZE = 16;
