// Copyright (C) 2025  Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and any partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
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// Subscription Agreement, the Altera Quartus Prime License Agreement,
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// agreement, including, without limitation, that your use is for
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// Generated by Quartus Prime Version 24.1 (Build Build 1077 03/04/2025)
// Created on Sun Apr 27 18:24:17 2025

UartTop UartTop_inst
(
	.clk(clk_sig) ,	// inout  clk_sig
	.data_byte(data_byte_sig) ,	// input [7:0] data_byte_sig
	.data_write(data_write_sig) ,	// input  data_write_sig
	.o_fifoFull(o_fifoFull_sig) ,	// output  o_fifoFull_sig
	.tx_pin(tx_pin_sig) 	// output  tx_pin_sig
);

defparam UartTop_inst.FIFOSIZE = 16;
