
/* UartClock
Outputs a n * 115200 Hz clock valid pulse from a 50MHz system clock
*/ 


module UartClock #(parameter OVERSAMPLING=8)
 (
  input i_clk,     // system clock
  output o_clk,     // uart clock (high for one i_clk cycle)
  output o_clk2    // uart clock for Rx operation (high for one i_clk cycle)
  );

  reg [31:0] acc = 0;
  reg [31:0] acc2 = 0;
  reg acc_tm1;
  reg acc2_tm1;
  
  localparam INCREMENT = 32'd9895605 * 4; //115200 *4 Baud
  // computed as: (2^32 * 115200) / 50_000_000  

  //localparam INCREMENT= 32'd10737418245/16; // clk/4  f. debugging
  localparam INCREMENT2 = INCREMENT*OVERSAMPLING; 


  always @(negedge i_clk) begin
		acc_tm1 <= acc[31];
		acc2_tm1 <= acc2[31];

    acc <= acc + INCREMENT;
    acc2 <= acc2 + INCREMENT2;
  end
  assign o_clk = acc[31] && ~acc_tm1;
  assign o_clk2 = acc2[31] && ~acc2_tm1;
    
endmodule
